1. Technical Field
The present disclosure relates to a method and system for energy conservation in general and, in particular, to a method and system for reducing power consumption within a data processing system. Still more particularly, the present disclosure relates to a method and system for reducing power consumption of a non-blocking cache within a data processing system.
2. Description of the Related Art
Lightweight notebook computers have become increasingly popular in recent years as many people are buying a notebook computer instead of a desktop computer as their primary computer. One of the many advantages a notebook computer offers is portability, and frequently, this portability is enhanced by its ability to operate under battery power. Needless to say, it is preferable to have a battery-powered notebook computer operate under battery power for an extended period of time before the battery needs recharging or replacing. Accordingly, from a design standpoint, it is important to reduce the power consumption of a notebook computer in order to extend the time during which the computer operates before any recharging or replacing of battery is required.
A microprocessor within a notebook computer typically accounts for up to one-third of the notebook computer's total power budget, which is around 15 W. Hence, a microprocessor originally designed for high-end desktop computers, which requires a 5V power supply and dissipates up to 16 W, is probably not a suitable candidate for notebook computer applications. For a microprocessor specifically designed to be utilized in notebook computer applications, at least three criteria must be met. First, there must be low power dissipation during the normal operation of the microprocessor. Second, there must be features for power management within the microprocessor, such as dynamic power management, and third, the most important of all from a user standpoint, the processing power of the microprocessor must be comparable to its desktop counterparts.
One of such low-power microprocessor design is disclosed in U.S. Pat. No. 5,420,808, entitled "Circuitry and Method for Reducing Power Consumption within an Electronic Circuit," and that patent is incorporated herein by reference thereto. The disclosed method under the above-referenced patent allows the microprocessor to consume less excess power without drastically sacrificing overall performance. In addition, the disclosed method is completely transparent to a user.
In light of U.S. Pat. No. 5,420,808, the present disclosure reveals a method for reducing power consumption of a non-blocking cache within a data processing system. The power consumption reduction method under the present disclosure may be implemented in any data processing system either independently or in conjunction with the method under U.S. Pat. No. 5,420,808. By implementing the method under the present disclosure in conjunction with the method under U.S. Pat. No. 5,420,808, an even lower power consumption level can certainly be achieved than utilizing the method under U.S. Pat. No. 5,420,808 alone.